This present invention relates to the field of digital-to-analog converters, and in particular to a digital-to-analog converter circuit that includes a ratiometric digital-to-analog converter.
Generally, digital-to-analog converters that provide ratiometric output values, require resistance dividers. “Ratiometric” refers to where an output voltage is proportionally related to the input voltage of the digital-to-analog converter. For example, where the input voltage doubles, the output voltage doubles. In order to reduce the surface area on circuit layouts for designing a digital-to-analog converter, which is necessary for analog adapted elements and a logic, a structure having two or three stages is necessary for a bit width of n is greater than six (n>6). There are a number of disadvantages in known digital-to-analog converters. For a precise digital-to-analog conversion, the necessary surface area for adapting resistances is related exponentially to the desired precision. In addition, in the case of segmented, resistive digital-to-analog converters, it is necessary to have a high precision, a small offset and a current compensation in order to reduce an inherently poor dynamic noise limitation performance (DNL performance). A low-impedance resistance string may interfere with the reference value, where the reference has a high-impedance output. In contrast, a high-impedance resistance string is more sensitive to switching and leakage currents, and requires a larger surface area. For a high-voltage ratiometric reference, for example, a supply voltage, and all switches which are joined with the conductor must be able to withstand high loads or stresses. As a result, disadvantageously a larger surface area is required for high-voltage MOS types of digital-to-analog converter circuits, and more leakage voltage occurs therewithin.
Therefore, there is a need for a digital-to-analog converter with ratiometric digital-to-analog conversion with reduced complexity.